D flipflop

Hii,

I am back again, this time you will see a lot of me.

this is the simulation of a D flip-flop.

Code:

module Add_half(sum,c_out,a,b);

    input   a,b;

    output  c_out,sum;

    xor(sum,a,b);

    and(c_out,a,b);

endmodule

Test Bench

module addtest;

    reg a,b;

    wire sum,c;

    

    Add_half Addhalf(.a(a),.b(b),.sum(sum),.c_out(c));

    

    initial

    begin

    $monitor  ($time,"a=%b b=%b sum=%b c=%b",a,b,sum,c);

    

        #5 a=0;b=0;

        #10 a=0;b=1;

        #15 a=1;b=0;

        #20 a=1;b=1;

        #25 a=1;b=1;

        

    end

endmodule

and the simulation waveform is